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NCP1600 Product Preview High Voltage PFC Controller with Standby Power Saving
The NCP1600 is an active power factor controller that functions as a boost pre-converter in off-line power supply applications. NCP1600 is optimized for low to medium power, high-density power supplies requiring a minimum board area, reduced component count and low power dissipation. The two comparators (C6, C7) are built in this device to improve power standby efficiency. With these two comparators, the PFC controller automatically switches itself in between normal mode and standby mode (skip or off mode) to save power consumption at light load. The NCP1600 can pursuit follower boost operation that is an innovative mode allowing a drastic size reduction of both the inductor and the power switch. Ultimately, the solution system cost is significantly lowered. NCP1600 can also be working in a traditional constant output voltage mode, any intermediary solutions can be easily implemented. This flexibility makes it ideal to optimally cope with a wide range of applications.
Features http://onsemi.com MARKING DIAGRAM
16 1 SO-16 D SUFFIX CASE 751B NCP1600 ALYW
A L Y W
= Assembly Location = Wafer Lot = Year = Work Week
PIN CONNECTIONS
AGnd 1 Vref 2 Restart Delay 3 FB_In 4 CS 5 Mir_Out 6 Vth 7 STB 8 (Top View) 16 Line 15 NC 14 Freq. Clamp 13 Vcon 12 CT 11 VCC 10 Gate 9 PGnd
* * * * * * * * * * * * * * * * * * * *
Loseless Off-Line Start-Up Standard Constant Output Voltage or "Follower Boost" Mode PFC Enter Skip Mode and Off Mode at Light Load Condition Selectable Switching Frequency Clamp Disable Pin to Stop PFC Operation Restart Delay Timer Input UVLO with Hysteresis Feedback Loop Open Detection Output Overvoltage Comparator Switch Mode Operation: Voltage Mode Latching PWM for Cycle-by-Cycle On-Time Control Constant On-Time Operation That Saves the Use of an Extra Multiplier Totem Pole Output Gate Drive Improved Regulation Block Dynamic Behavior Internally Trimmed Reference Current Source Internal Leading Edge Blanking (LEB) for Noise Immunity Monitor/TV Power Supplies PC Power Supplies Notebook PC Adapters Medium Power Adapters
ORDERING INFORMATION
Device NCP1600D Package SO-16 Shipping 48 Units/Rail
Typical Applications
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. This document, and the information contained herein, is CONFIDENTIAL AND PROPRIETARY and the property of Semiconductor Components Industries, LLC., dba ON Semiconductor. It shall not be used, published, disclosed or disseminated outside of the Company, in whole or in part, without the written permission of ON Semiconductor. Reverse engineering of any or all of the information contained herein is strictly prohibited. E 2002, SCILLC. All Rights Reserved.
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
(c) Semiconductor Components Industries, LLC, 2002
1
June, 2002 - Rev. 0
Publication Order Number: NCP1600/D
CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE
NCP1600
Line
Q1 RD 3 AGnd 1 -60 mV Output + C2 IREF (205 mA) ICS2 + - ON L.E.B. BK3 SW2 CS 5 11 V C5 + Output NT1 3 UVP AND1 12 15 pF 11 V SW1 ON IO IREF - Output + C7 0.5 V - Output C6 -+ ICS1 Iosc-ch=2*Io*Io*/Iref Current Mirror BK6 Current Mirror + 11 V Output_Ctrl 1V Output OVP - + C4 + - IO IO IREF Gnd BK5 + - C3 + 3.8 V - Output VREF VREG IO NOR1 Output_Ctrl Frequency Clamp BK4 OR1 Q2 Output_Ctrl BK2 Timer Q R VREF IREF BK1 VREF Enable RS Latch S R R R Q FF1 3 4 2 1 NOR2 5 Q Th_Stdwn Q3 High IREF UVLO C1 + + - 15 V/10 V Z15V
VCC 11
Gate 10 Q4 PGnd 9 FC 14 VCon 13
VREF 2
CT 12
FB In 4
STB 8 + - Vth 7 Mir Out 6
Figure 1. Detailed Block Diagram
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2
"Suffer 25 Vmax"
VREF
16 NCP1600
NCP1600
90~264 Vac + - 4 2 3 0.22 m, 400 V + U2 DF06S 1
CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE
+
Line VREF "Suffer 25 Vmax"
NCP1600
Q1 Output_Ctrl
16
RD + 3
+
Q2
BK2 Timer Q R VREF IREF
BK1 VREF Enable IREF C1 UVLO
Z15V
AGnd 1 -60 mV C2 IREF (205 mA) ICS2 + - ON L.E.B. BK3 SW2 CS 5 11 V C5 NOR1
RS Latch
+
+ - 15 V/10 V Q3
VCC 11
+ -
Output
S R
Q FF1 Th_Stdwn 3 4 2 NOR2 1
R R Q
High Q4
Gate 10 PGnd 9 FC 14 VCon 13
VREF + 0.1 mF 2
5
OR1 Output_Ctrl Frequency Clamp BK4 NT1 Output 3 AND1 12 1V Output Output UVP
+
15 pF
+-
CT 12 + 11 V Output_Ctrl ON
+ C3 3.8 V
-+
-
OVP BK5
VREF VREG IO IO IO IO IREF 11 V IREF Gnd FB In 4
+
+ C4
4.7 kW
SW1
STB 8 + - Vth 7 Mir Out 6
C7 0.5 V
+
Output Output C6
-
+
-+
ICS1 Iosc-ch=2*Io*Io*/Iref Current Mirror BK6 Current Mirror
Figure 2. Representative Application Circuit
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NCP1600
PIN FUNCTION DESCRIPTIONS
Pin 1 2 3 4 5 Symbol AGnd Vref Restart Delay FB_Input CS Analog Ground. Output reference voltage 6.5 V. This pin is high impedance input and the pin connecting R,C to setup the Delay Time. After this delay time, IC will turns off internal start-up FET Q1 during start-up. This pin designed to receive a current that is proportional to pre-converter output voltage. This pin is designed to receive a negative voltage signal proportional to the current flowing through the inductor. This information is generally built using a sense resistor. The Zero Current Detection prevents any restart as long as the pin 5 voltage is below (-60 mV). This pin is also used to perform the peak current limitation. The resistor connected between the pin and the current-sense-resistor programs the overcurrent threshold. The Current Mirror output one current which is same to pin 4 (FB_Inut) input current. This current information is used for disabling PFC boost pre-converter at standby, Overvoltage and Undervoltage protection. This pin divided the reference voltage to design the minimum threshold voltage of PFC Output Voltage during standby. PFC boost pre-converter standby pin. The PFC enters stand-by mode (PFC boost pre-converter enter both skip mode and off mode) when voltage at this pin falls below 0.5 V. This pin also can be connected to PWM feedback pin. Power Ground. The gate drive current capability is suited to drive an IGBT or a power MOSFET. This pin is the positive supply of the IC. The circuit turns on when VCC becomes higher than 15 V, the operating range after start-up being 8.0 V up to 30 V. The circuit uses an on-time control mode. This on-time is controlled by comparing the CT voltage to the V control voltage. CT is charged by the squared feedback current. This pin makes available the regulation block output. The capacitor connected between this pin and ground, adjusts the control bandwidth. It is typically set below 20 Hz to obtain a non-distorted input current. By connecting R.C. on this pin to setup the maximum switch frequency. No connection. This pin connects directly to the rectified AC line voltage source. Description
6
Mir_Out
7 8
Vth STB
9 10 11 12 13
PGnd Gate VCC CT Vcon
14 15 16
Frequency Clamp NC Line
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NCP1600
MAXIMUM RATINGS
Rating Power Supply Voltage (Transient) Power Supply Voltage (Operating) Line Voltage Input Voltage Frequency Clamp Input Restart Diode Current Output Current, Source or Sink Power Dissipation and Thermal Characteristic D Suffix, Plastic Package Case 751B Maximum Power Dissipation @ TA = 70_C Thermal Resistance, Junction-to-Air Operating Junction Temperature Storage Temperature Range NOTE: ESD data available upon request. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) "2.0 kV per JEDEC standard: JESD22-A114. Machine Model (MM) "200 V per JEDEC standard: JESD22-A115. 2. Latch-up Current Maximum Rating: 150 mA per JEDEC standard: JESD78. 3. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J-STD-020A. Symbol VCC VCC VLine Vin1 Vin2 Iin Io
CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE
Value 30 25 500 -1.0 to +10 -1.0 to +30 5.0 1.0
Unit V V V V V mA A
PD RJA TJ Tstg
550 145 150 -55 to +150
mW _C/W _C _C
ELECTRICAL CHARACTERISTICS (VCC = 17 V, for typical values TA = 25C, for min/max values TA = -25 to +125C)
Characteristic REGULATION SECTION Regulation High Current Reference Ratio (Regulation Low Current Reference)/Iref Vcontrol Impedance Feedback Pin Clamp Voltage @ IFB = 100 mA Feedback Pin Clamp Voltage @ IFB = 200 mA VOLTAGE REFERENCE Voltage Reference (IO = 0 mA) Line Regulation (VCC = 11 V to 25 V) Load Regulation (Io = 0 to 5.0 mA) Total Output Variation Over Line, Load and Temperature Maximum Output Current FREQUENCY CLAMP Frequency Clamp Input Threshold Frequency Clamp Capacitor Reset Current (VFC = 0.5 V) Frequency Clamp Disable Voltage VCC HYSTERESIS Start-up Threshold (VCC Increasing) Minimum Operating Voltage After Turn-On (VCC Decreasing) Hysteresis TIMER Minimum Off Time toff 1.5 2.1 2.7 ms Vth(ON) VShutdown VH 14 9.0 - 15 10 5.0 16 11 - V V V Vth (FC) IReset VDFC 1.9 0.5 7.0 2.0 1.7 7.5 2.1 4.0 8.0 V mA V Vref Regline Regload Vref IO 6.4 - - 6.25 5.0 6.5 5.0 5.0 6.5 10 6.6 125 125 6.75 - V mV mV V mA Iref Ireg-L/Ireg-H Zvcontrol VFB-100 VFB-200 195 0.965 - 1.5 2.0 200 0.97 300 2.1 2.6 205 0.98 - 2.5 3.0 mA - k V Symbol Min Typ Max Unit
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NCP1600
ELECTRICAL CHARACTERISTICS (continued) (VCC = 17 V, for typical values TA = 25C, for min/max values TA = -25 to +125C)
Characteristic OSCILLATOR SECTION Maximum Oscillator Swing Charge Current @ IFB = 100 mA Charge Current @ IFB = 200 mA Ratio Multiplier Gain Over Maximum Swing Average Internal Oscillator Pin Capacitance Over Oscillator Maximum Swing (CT Voltage Varying From 0 up to 1.5 V) Discharge Time CURRENT SENSE SECTION Zero Current Detection Comparator Threshold Negative Clamp Level (Ics-pin = -1.0 mA) Bias Current @ Vcs = Vzcd-th Propagation Delay (Vcs > Vzcd-th) to Gate Drive High Current Sense Pin Internal Current Source Leading Edge Blanking Duration Overvoltage Protection Propagation Delay (Vcs < Vzcd-th to Gate Drive Low) DRIVE OUTPUT Source Resistance (CT = 0 V, VGate = 14 V) Sink Resistance (CT = 2.0 V, VGate = 1.0 V) Output Voltage Rise Time (10%-90%) (CL = 1.0 nF) Output Voltage Fall Time (90%-10%) (CL = 1.0 nF) Output Voltage in Undervoltage (VCC = 10 V, Isink = 1.0 mA) OVERVOLTAGE PROTECTION SECTION Overvoltage Protection Threshold (C4 Comparator) Propagation Delay (Vpin6 > 3.8 V to Gate Drive Low) UNDERVOLTAGE PROTECTION SECTION Undervoltage Protection Threshold (C3 Comparator) Propagation Delay (Vpin6 < 1.0 V to Gate Drive Low) STANDBY SECTION Standby Threshold (C7 Comparator) Propagation Delay (Vpin8 < 0.5 V to Gate Drive Low) THERMAL SHUTDOWN SECTION Thermal Shutdown Threshold Hysteresis TOTAL DEVICE Line Start-up Current (VCC = 0 V, VLine = 50 V) Line Operating Current (VCC = VTH(ON), VLine = 50 V) VCC Dynamic Operating Current (50 kHz, CL = 1.0 nF) VCC Static Operating Current (Io = 0) Line Pin Leakage (VLINE = 500 V) ISU IOP ICC ILine 5.0 3.0 - - - 16 12.9 5.3 3.0 30 25 20 8.5 - 80 mA mA mA mA Tstdwn DTstdwn - - 150 30 - - _C _C VC7 Tovp 0.45 - 0.5 500 0.55 - V ns VC3 TUVLO 0.95 - 1.0 500 1.05 - V ns VC4 Tovp 3.75 - 3.8 500 3.85 - V ns ROH ROL tr tf VO(UV) 17 4.0 - - - 25 10 50 50 - 40 17 200 200 0.25 ns ns V VZCD-th CI-neg Ib-cs TZCD IOCP LED Tocp -90 - -0.2 - 192 - 100 -60 -0.7 - 500 205 400 160 -30 - - - 218 - 240 mV V mA nS mA nS nS DVT Icharge-100 Icharge-200 KOSC Cint Tdisch 1.4 87.5 350 5600 10 - 1.5 100 400 6400 15 0.5 1.6 112.5 450 7200 20 1.0 V mA mA 1/(V,A) pF mS Symbol Min Typ Max Unit
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NCP1600
DETAILED OPERATING DESCRIPTION Introduction The need of meeting the requirements of legislation on line current harmonic content, results in an increasing demand for cost effective solutions to comply with the Power Factor regulations. This data sheet describes a monolithic controller specially designed for this purpose. Most off-line appliances use a bridge rectifier associated to a huge bulk capacitor to derive raw DC voltage from the utility AC line.
Rectifiers AC Line + Bulk Storage Capacitor Converter
CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE
This occurs near the line voltage peak and results in a high charge current spike. Consequently, a poor power factor (in the range of 0.5-0.7) is generated, resulting in an apparent input power that is much higher than the real power.
Vpk Rectified DC 0 Line Sag AC Line Voltage 0 AC Line Current
Load
Figure 4. Line Waveforms Without PFC Figure 3. Typical Circuit Without PFC
This technique results in a high harmonic content and in poor power factor ratios. In effect, the simple rectification technique draws power from the mains when the instantaneous AC voltage exceeds the capacitor voltage.
Rectifiers AC Line High Frequency Bypass Capacitor
Active solutions are the most popular way to meet the legislation requirements. They consist of inserting a PFC pre-regulator between the rectifier-bridge and the bulk capacitor. This interface is, in fact, a step-up SMPS that outputs a constant voltage while drawing a sinusoidal current from the line.
Converter
PFC Preconverter
+ MC33260
Bulk Storage Capacitor
Load
Figure 5. PFC Preconverter
The NCP1600 was developed to control an active solution with the goal of increasing its robustness while lowering its global cost. Operating Description The NCP1600 is optimized to just as well drive a free running as a synchronized discontinuous voltage mode. It also features valuable protections (overvoltage and undervoltage protection, overcurrent limitation, ...) that make the PFC pre-regulator very safe and reliable while requiring very few external components. In particular, it is able to safely face any uncontrolled direct charges of the output capacitor from the mains which occur when the output voltage is lower than the input voltage (start-up, overload, ...). In addition to the low count of elements, the circuit can be running in an innovative mode named "Follower Boost" that permits significant reduction of the size of the pre-converter inductor and power MOSFET. With this technique, the output regulation level is not forced to a constant value, but can vary according to the AC line
amplitude and to the output power. The gap between the output voltage and the AC line is then lowered, what allows the pre-converter inductor and power MOSFET size reduction. Finally, this method brings significant cost reduction. A description of the functional blocks is given below.
Regulator Section
Connecting a resistor between the output voltage to be regulated and the Pin 4, a feedback current is obtained. Typically, this current is built by connecting a resistor between the output voltage and the Pin 4. Its value is then given by the following equation:
Ipin4 + Vo * Vpin4 Ro
where: Ro is the feedback resistor, Vo is the output voltage, Vpin4 is the Pin 4 clamp value.
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NCP1600
IREF + - ICS1 Iosc-ch=2*Io*Io/Iref Output_Ctrl
The feedback current is compared to the reference current so that the regulation block outputs a signal following the characteristic depicted in Figure 6. According to the power and the input voltage, the output voltage regulation level varies between two values (Vo)reg-L and (Vo)reg-H corresponding to the Ireg-L and Ireg-H levels.
Regulation Block Output 1.5 V 12 + 11 V 15 pF SW1
CT
IO Ireg-L (97%Iref) Ireg-H (Iref)
Figure 6. Regulation Characteristic
Figure 7. Oscillator
The feedback resistor must be chosen so that the feedback current should equal the internal current source Ireg-H when the output voltage exceeds the chosen upper regulation voltage [(Vo) reg-H]. Consequently:
Ro + (Vo)regH * Vpin4 IregH
The oscillator charge current is dependent on the feedback current (Io). In effect:
Icharge + 2 Io2 Iref
In practice, Vpin3 is small compared to (Vo)regH and this equation can be simplified as follows (IregH being also replaced by its typical value 200 m):
Ro [ 5 (Vo)regH in kW
where: Icharge is the oscillator charge current, Io is the feedback current (drawn by pin 4), Iref is the internal reference current (200 m). So, the oscillator charge current is linked to the output voltage level as follows:
Icharge + 2 (Vo * Vpin4)2 Ro2 Iref
The regulation block output is connected to the Pin 13 through a 300 KW resistor. The Pin 13 voltage (Vcontrol) is compared to the oscillator saw-tooth for PWM control. An external capacitor must be connected between Pin 13 and ground, for external loop compensation. The bandwidth typically set below 20 Hz so that the regulation block output should be relatively constant over a given AC line cycle. This integration that results in a constant on-time over the AC line period, prevents the mains frequency output ripple from distorting the AC line current.
Oscillator Section
where: Vo is the output voltage, Ro is the feedback resistor, Vpin4 is the Pin 4 Clamp voltage. In practice, Vpin4 that is in the range of 2.5 V, is very small compared to Vo. The equation can then be simplified by neglecting Vpin4:
Icharge [ Vo2 Ro2 Iref 2
* Charge Phase: The oscillator capacitor voltage grows
up linearly from its bottom value (ground) until it exceeds Vcontrol (regulation block output voltage). At that moment, the PWM latch output gets low and the oscillator discharge sequence is set. Discharge Phase: The oscillator capacitor is abruptly discharged down to its valley value (0 V). Waiting Phase: At the end of the discharge sequence, the oscillator voltage is that maintained in a low state until the PWM latch is set again.
The oscillator consists of three phases:
* *
It must be noticed that the oscillator terminal (Pin 12) has an internal capacitance (Cint) that varies versus the Pin 12 voltage. Over the oscillator swing, its average value typically equals 15 pF (min 10 pF, max 20 pF). The total oscillator capacitor is then the sum of the internal and external capacitors.
Cpin12 + CT ) C int
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NCP1600
PWM Latch Section
CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE
The NCP1600 operates in voltage mode: the regulation block output Vcontrol (Pin 13 voltage) is compared to the oscillator saw-tooth so that the gate drive signal (Pin 10) is high until the oscillator ramp exceeds Vcontrol. The on-time is then given by the following equation:
Cpin12 Vcontrol ton + Icharge
Refer to Electrical Characteristics, Oscillator Section. Then:
ton max + Cpin12 Ro2 Kosc Vo2
This equation shows that the maximum on-time is inversely proportional to the squared output voltage. This property is used for follower boost operation (refer to Follower Boost section).
Current Sense Block
where: ton is the on-time, Cpin12 is the total oscillator capacitor (sum of the internal and external capacitor), Icharge is the oscillator charge current (Pin 12 current), Vcontrol is the Pin 13 voltage (regulation block output). Consequently, replacing Icharge by the expression given in the Oscillator Section:
ton + Ro2 Iref Cpin12 2 V2o Vcontrol
The inductor current is converted into a voltage by inserting a ground referenced resistor (Rcs) in series with the input diodes bridge (and the input filtering capacitor). Therefore a negative voltage proportional to the inductor current is built:
Vcs + * (Rcs IL)
where: IL is the inductor current, Rcs is the current sense resistor, Vcs is the measured Rcs voltage. The negative signal Vcs is applied to the current sense through a resistor ROCP. This pin is internally protected by a negative clamp (-0.7 V) that prevents substrate injection. As long as the Pin 5 voltage is lower than (-60 mV), the Current Sense comparator resets the PWM latch to force the gate drive signal low state. In that condition, the power MOSFET cannot be on. During the on-time, the Pin 5 information is used for the overcurrent limitation while it serves the zero current detection during the off time.
One can notice that the on-time depends on Vo (pre-converter output voltage) and that the on-time is maximum when Vcontrol is maximum (1.5 V typically). At a given Vo, the maximum on-time is then expressed by the following equation:
ton max + Ro2 Iref Cpin12 2 2 Vcontrol max Vo2 Vcontrol max
This equation can be simplified replacing:
Iref by Kosc
Switch Drive Time Inductor Current
Switch Drive VOCP CS Pin Voltage
Zero Current Detection (-60 mV) VOCP = ROCP X IOCP
Figure 8. Current Sensing http://onsemi.com
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CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE
NCP1600
the circuit gate drive signal is kept in low state. Consequently, no power MOSFET turn on is possible until the inductor current is measured as smaller than (60 mV/Rcs) that is, the inductor current nearly equals zero.
Zero Current Detection
The Zero Current Detection function guarantees that the MOSFET cannot turn on as long as the inductor current hasn't reached zero (discontinuous mode). The Pin 5 voltage is simply compared to the (-60 mV) threshold so that as long as Vcs is lower than this threshold,
1
DF06S + 90~264 Vac - 4
U2 3 IREF (205 mA) ICS2 + - ON L.E.B.
-60 mV + C2 Output S 0 0 0 R R R Q FF1 Q
2
BK3 1 SW2 ROCP RCS CS 5 11 V Output_Ctrl
Figure 9. Current Sense Block OCP (Overcurrent Protection) ROCP kW Rcs W
During the power switch conduct (i.e. when the Gate Drive pin voltage is high), a current source is applied to the Pin 5. A voltage drop VOCP is then generated across the resistor ROCP that is connected between the sense resistor and the Current Sense pin (refer to Figure 9). So, instead of Vcs , the sum(Vcs + VOCP) is compared to (-60 mV)and the maximum permissible current is the solution of the following equation:
* (RCS Ipk(max)) ) VOCP + * 60 mV
Ipk(max) [
0.205 A
where: Ipk(max) is the maximum allowed current, Rcs is the sensing resistor. The overcurrent threshold is then:
Ipk(max) + (ROCP IOCP) ) (60 Rcs 10 * 3)
Consequently, the ROCP resistor can program the OCP level whatever the Rcs value is. This gives a high freedom in the choice of Rcs. In particular, the inrush resistor can be utilized. An LEB (Leading Edge Blanking) has been implemented. This circuitry disconnects the Current Sense comparator from Pin 5 and disables it during the first 400 ns of the power switch conduction. This prevents the block from reacting on the current spikes that generally occur at power switch turn on. Consequently, proper operation does not require any filtering capacitor on Pin 5.
OVP (Overvoltage Protection)
where: ROCP is the resistor connected between the pin and the sensing resistor (Rcs), IOCP is the current supplied by the Current Sense pin when the gate drive signal is high (power switch conduction phase). IOCP equals 205 mA typically. Practically, the VOCP offset is high compared to 60 mV and the precedent equation can be simplified. The maximum current is then given by the following equation:
Referring to Figure 10, Current Mirror output Io is relating to PFC output voltage. The current Io flows into the external resistor and a voltage drop developed across Pin 6. This voltage then is compared with the Overvoltage Protection Threshold, VC4, 3.8 V, when the voltage is higher than the VC4, the OVP comparator, C4 will be enabled and the PFC gate drive disabled as a result to keep the bulk capacitor voltage below the set level. By selecting the value of the external resistor, the OVP voltage can then be determined. With this feature, the maximum bulk capacitor voltage can be set to value below 400 V so that lower cost bulk capacitor can be used.
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NCP1600
PFC Output Voltage 1.8 MW 0.5 W
CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE
Output OVP - + C4 + 3.8 V - Mir Out 6 18 k IO Current Mirror BK6 Current Mirror 11 V 4
Output OVP UVP - + C4 + 1V 3.8 V - Mir Out 6 18 k IO Current Mirror
Output + - C3 + - 11 V 4
PFC Output Voltage 1.8 MW 0.5 W
FB In
FB In
Current Mirror BK6
Figure 10. Overvoltage Protection
Figure 11. Undervoltage Detection
Undervoltage Protection and Feedback Loop Open Detection
Switching Frequency Clamp
Refer to Figure 11, similarly, the PFC function will be bypassed until Pin 6 voltage exceed 1.0 V. This feature is used to avoid the PFC drawing high current while the line voltage fall below a reasonable level in order to protect the power elements. This protection feature is also applicable for Feedback Loop Open Detection, i.e. while the feedback resistor is open, no current flowing into the FB_In pin (Pin 4), hence the voltage across Pin 6 will be diminished and the protection will be activated.
Refer to Figure 12, Switching Frequency Clamp. The frequency clamp function can be disabled by pulling the FC pin voltage higher than frequency clamp threshold. While the frequency clamp function is disabled, the PFC gate drive turn-on depends on zero-current-detection of CS pin. By connecting RC to frequency clamp pin, the PFC gate drive turn-on depend on both FC pin voltage and CS pin's zero-current-detection. When FC pin voltage reach its threshold, PFC gate drive turn-on by zero-current- detection of CS pin.
FC Pin
PFC Gate
CS Pin -60 mV Zero Current Detection
Figure 12. Switch Frequency Clamp
For best results, the minimum off-time, determined by the values of R and C on FC pin, should be chosen so that ts(min) = ton + toff(FC). Output drive is inhibited when the voltage at the frequency clamp input is less than 2.0 V. When the output drive is high, C is discharged through an internal 100 mA current source. When the output drive switches low, C7 is charged through RFC. The drive output
is inhibited until the voltage across CFC reaches 2.0 V, establishing a minimum off-time where:
toff + * (RFC)(CFC) log e 1 * 2 Vref
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NCP1600
Thermal Shutdown
Output Section
The output stage contains a totem pole optimized to minimize the cross conduction current during high speed operation. The gate drive is kept in a sinking mode whenever the Undervoltage Lockout is active. The rise and fall times have been controlled to typically equal 50 ns while loaded by 1.0 nF.
Reference Section
An internal thermal circuitry is provided to disable the circuit gate drive and then to prevent it from oscillating, if the junction temperature exceeds 150_C typically. The output stage is again enabled when the temperature drops below 120_C typically (30_C hysteresis).
Follower Boost Operation
An internal reference current source (Iref) is trimmed to be "2.5% accurate over the temperature range (the typical value is 200 mA). Iref is the reference used for the regulation. An internal reference voltage (Vref) is trimmed to be "1.53% accurate over the temperature range (the typical value is 6.5 V).
Traditional PFC pre-converters provide the load with a and regulated voltage that generally equals 230 V or according to the mains type (U.S., European, or universal). In the "Follower Boost" operation, the pre-converter output regulation level is not fixed but varies linearly versus the AC line amplitude at a given input power.
Traditional Output
VO (Follower Boost)
VAC
Load
Figure 13. Follower Boost Characteristics
This technique aims at reducing the gap between the output and the input voltages to minimize the boost efficiency degradation.
Follower Boost Benefits
*
*
The boost presents two phases: The on-time during which the power switch is on. The inductor current grows up linearly according to a slope (Vin/Lp), where V in is the instantaneous input voltage and Lp the inductor value. The off-time during which the power switch is off. The inductor current decreases linearly according to the slope (Vo-Vin)/Lp, where Vo is the output voltage. This sequence that terminates when the current equals zero, has a duration that is inversely proportional to the gap between the output and input voltages.
Consequently, the off-time duration becomes longer in follower boost. Consequently, for a given peak inductor current, the longer the off time, the smaller power switch duty cycle and then its conduction dissipation. This is the first benefit of this technique: the MOSFET on-time losses are reduced. The increase of the off time duration also results in a switching frequency diminution (for a given inductor value). Given that in practice, the boost inductor is selected big enough to limit the switching frequency down to an acceptable level, one can immediately see the second benefit of the follower boost: it allows the use of smaller, lighter and cheaper inductors compared to traditional systems. Finally, this technique utilization brings a drastic system cost reduction by lowering the cost of both the inductor and the power switch.
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NCP1600
Traditional Preconverter Follower Boost Preconverter IL Ipk
CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE
where: Vpk is the peak AC line voltage, Lp is the inductor value, Pin is the input power. Combining the two equations, one can obtain the Follower Boost equation:
time
Vo +
Vin IL IL Vin Vin Vout Output Voltage Input Power Vin
Ro 2
Kosc
Cpin12 Lp Pin
Vpk
Consequently, a linear dependency links the output voltage to the AC line amplitude at a given input power.
The Regulation Block is Active (VAC)max
The Power Switch is On
The Power Switch is Off
VAC Pin
Figure 14. Off-Time Duration Increase
Output Voltage Input Power
Follower Boost Implementation
In the NCP1600, the on-time is controlled differently according to the feedback current level. Two areas can be defined: * When the feedback current is higher than IregL (refer to regulation section), the regulation block output (Vcontrol) is modulated to force the output voltage to a desired value. * On the other hand, when the feedback current is lower than IregL, the regulation block output and therefore, the on-time are maximum. As explained in PWM Latch Section, the on-time is then inversely proportional to the output voltage square. The Follower Boost is active in these conditions in which the on-time is simply limited by the output voltage level. Note: In this equation, the feedback pin voltage (Vpin1) is neglected compared to the output voltage (refer to the PWM Latch Section).
ton + ton max + Cpin12 Ro2 Kosc Vo2
(VAC)min VO ton = k/VO2
ton
on-time
Figure 15. Follower Boost Characteristics
where: Cpin12 is the total oscillator capacitor (sum of the internal and external capacitors - Cint + CT), Kosc is the ratio (oscillator swing over oscillator gain), Vo is the output voltage, Ro is the feedback resistor. On the other hand, the boost topology has its own rule that dictates the on-time necessary to deliver the required power:
ton + 4 Lp Vpk2 Pin
The behavior of the output voltage is depicted in Figures 15 and 16. In particular, Figure 15 illustrates how the output voltage converges to a stable equilibrium level. First, at a given AC line voltage, the on-time is dictated by the power demand. Then, the follower boost characteristic makes correspond one output voltage level to this on-time. Combining these two laws, it appears that the power level forces the output voltage. One can notice that the system is fully stable: * If an output voltage increase makes it move away from its equilibrium value, the on-time will immediately diminish according to the follower boost law. This will result in a delivered power decrease. Consequently, the supplied power being too low, the output voltage will decrease back. * In the same way, if the output voltage decreases, more power will be transferred and then the output voltage will increase back.
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CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE
NCP1600
VO = VPK
VO (Pin)min
Regulation Block is Active
Consequently,
CT w * Cin ) int 4 Kosc Lp Pin max Ro2 Vpk2 Vo regL2
Pin (Pin)max
Using IregL (regulation block current reference), this equation can be simplified as follows:
CT w * Cin ) int 4 Kosc Lp Pin max Vpk2 IregL2
non usable area
In the Follower Boost case, the oscillator capacitor must be chosen so that the wished characteristics are obtained. Consequently, the simple choice of the oscillator capacitor enables the mode selection.
Standby Operation
VAC VacLL VAC VacHL
Figure 16. Follower Boost Output Voltage Mode Selection
The operation mode is simply selected by adjusting the oscillator capacitor value. As shown in Figure 16, the output voltage first has an increasing linear characteristic versus the AC line magnitude and then is clamped down to the regulation value. In the traditional mode, the linear area must be rejected. This is achieved by dimensioning the oscillator capacitor so that the boost can deliver the maximum power while the output voltage equals its regulation level and this, whatever the given input voltage. Practically, that means that whatever the power and input voltage conditions are, the follower boost would generate output voltages values higher than the regulation level, if there was no regulation block. In other words, if regL is the low output regulation level:
R Vo regL v o 2 Kosc CT ) Cint in Lp Pin max Vpk
PFC boost pre-converter entering standby mode depends on the STB (Standby) pin voltage (Pin 8 voltage) which is high impedance input and can be directly connected to PWM section's Opto-coupler output to derive PWM output load information. PFC boost pre-converter will enter Standby mode when the voltage at this pin falls below 0.5 V. While the output of C7 is low, the PFC will stay in normal operation and the AND1 gate output will keep low for all the time. When the STB pin voltage falls below the threshold, 0.5 V, the output of C7 will go high and the output of AND1 gate will depends on the output of C6. The current flowing from the current mirror on Pin 4 is equal to FB-In pin (Pin 4) current which derives from Bulk Capacitor voltage at the output. PFC pre-converter will be disabled when the voltage at Pin 6 is higher than the voltage at Pin 7. The minimum PFC output voltage can be set by Pin 7 voltage during standby mode. This voltage can be derived from the Vref (Pin 2) by a potential divider network. During standby operation, the PFC boost pre-converter will enter skip mode when AC input voltage falls below this pre-set value, the minimum PFC output voltage and PFC boost pre-converter will enter off mode when AC input voltage higher than the pre-set minimum PFC output voltage.
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NCP1600
PACKAGE DIMENSIONS
CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE
SO-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE
NCP1600
GreenLine is a trademark of Motorola, Inc.
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NCP1600/D

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